Senior ASIC Packaging SI/PI Lead

Cisco; Boston (MA); Remote; USD 150,000 - 210,000; Full time

Job summary

Cisco is seeking a highly qualified Signal and Power Integrity Technical Lead for our San Jose-based hardware engineering team. The role supports remote applicants within the United States and focuses on advancing ultra-high-speed signaling and robust SI/PI methods across ASIC packaging.

Responsibilities include leading design rule development, SI/PI analyses, and post-layout reporting, while mentoring engineers and driving cross-functional collaboration to meet performance goals.

Qualifications

• Bachelor's in Electrical Engineering with 8+ years SI/PI experience (or MS 6+ yrs, PhD 3+ yrs).
• Experience with high-speed design principles and 56G PAM4 SerDes architectures.
• Proficient in pre/post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, Keysight ADS.
• Layout review and physical validation using Cadence APD and Ansys EM flows.
• Circuit analysis using SPICE for modeling and verification.

Responsibilities

• Develop and document design rules for ultra-high-speed signaling with power/area goals.
• Analyze substrate SI/PI and advise layout teams for optimal interposer, substrate, and PCB solutions.
• Design, document, and develop ASIC packages for high-volume, high-quality releases with post-layout reporting.
• Collaborate with system partners and leads to resolve complex SI/PI issues using advanced rules.
• Lead architecture discussions and reviews of complex IC and analog/mixed-signal designs.
• Mentor SI team, junior engineers, and influence packaging/hardware teams.
• Promote design reviews, postmortems, and continuous improvement across multi-disciplined teams.

Skills

High-Speed Design

SI/PI Simulation

Layout Review

Circuit Analysis

Transmission Line Theory

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

SPICE

Job description

Cisco is seeking a highly qualified Signal and Power Integrity Technical Lead for our San Jose-based hardware engineering team. The role supports remote applicants within the United States and focuses on advancing ultra-high-speed signaling and robust SI/PI methods across ASIC packaging.

Responsibilities include leading design rule development, SI/PI analyses, and post-layout reporting, while mentoring engineers and driving cross-functional collaboration to meet performance goals.