SI/PI Lead for ASIC Packaging

Cisco Systems, Inc.

San Jose (CA)

Hybrid

USD 214,000 - 310,000

Full time

5 days ago

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Job summary

Cisco Silicon One is seeking a Signal and Power Integrity Technical Leader in San Jose to drive ASIC packaging, SI/PI analysis, and high-speed interconnect design. You will lead a team to define rules, verify designs, and collaborate with layout and system partners to achieve optimal performance and reliability.

The role requires extensive lab work, ASIC tape-out experience, and expertise in PAM4, SerDes, and 2.5D packaging.

Qualifications

Bachelor's degree in Electrical Engineering with 10+ years of SI/PI experience, or advanced degrees with progressive experience.
Experience with multiple high-speed ASIC tape-outs from a package perspective.
Experience with 56G PAM4+, SerDes, channel modeling, BER prediction, and high-frequency electromagnetics.
Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
Experience with SPICE and practical lab validation.

Responsibilities

Define, design and verify ASIC packaging for Cisco platforms, guiding SI/PI effort.
Develop and document rules for ultra-high-speed signaling meeting power, performance, and area goals.
Analyze substrate SI/PI and coordinate with layout to optimize interposer, substrate and PCB."
Design, document and develop ASIC packages for high-volume, high-quality release including post-layout extraction.
Collaborate with system partners to resolve complex IP-level SI/PI issues using advanced rules.
Lead architecture discussions and contribute to high-performance ASIC/package development.
Mentor the SI team and promote design reviews and continuous improvement across related teams.