Remote SI/PI Technical Lead – High-Speed ASIC Packaging

Cisco; Allen (TX); Hybride; USD 214 000 - 310 000; Plein temps

Résumé du poste

Cisco is seeking a Signal and Power Integrity Technical Leader in the San Jose area. The role leads the Silicon Packaging SI/PI team to define, design, and verify packaging for high-performance ASICs.

You will develop rules for ultra-high-speed signaling and collaborate across layout, system partners, and design leads to resolve complex issues. The ideal candidate has extensive SI/PI experience with high-speed SerDes, PAM4, and advanced packaging technologies, and will mentor junior engineers

Qualifications

• Bachelor's degree in Electrical Engineering required.
• Master's degree or PhD with relevant SI/PI experience preferred.
• 10+ years (or 8+ with Masters, 5+ with PhD) of SI/PI experience.

Responsabilités

• Lead ASIC packaging SI/PI team to define, design and verify packaging.
• Develop design rules for ultra-high-speed signaling ensuring power, performance, and area goals.
• Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB.
• Design ASIC packages for high-volume release including post-layout extraction.

Connaissances

56G PAM4

High-speed SerDes

Channel modeling

BER prediction

Transmission line theory

Electromagnetics

Formation

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Outils

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Description du poste

Cisco is seeking a Signal and Power Integrity Technical Leader in the San Jose area. The role leads the Silicon Packaging SI/PI team to define, design, and verify packaging for high-performance ASICs.

You will develop rules for ultra-high-speed signaling and collaborate across layout, system partners, and design leads to resolve complex issues. The ideal candidate has extensive SI/PI experience with high-speed SerDes, PAM4, and advanced packaging technologies, and will mentor junior engineers