Signal & Power Integrity Lead for ASIC Packaging

Cisco Systems, Inc; United States; Remote; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Disability coverage

Life insurance

RSU grants eligibility

Paid vacation time

Paid holidays

Volunteer days

Job summary

Cisco Silicon One seeks a Signal and Power Integrity Technical Leader to guide ASIC packaging development and lead the SI team in defining, designing and verifying packaging for high-volume Cisco platforms.

You will develop rules for ultra-high-speed signaling, ensure power/performance targets, and collaborate with layout and system partners to resolve complex issues while mentoring junior engineers and driving continuous process improvements.

Qualifications

• Bachelor's degree in Electrical Engineering and 12+ years of relevant signal and/or power integrity experience, or Master’s with 8+ years, or PhD with 5+ years.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics with impedance understanding.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Define, design and verify ASIC packaging to meet power, performance and area goals.
• Develop design rules for ultra-high-speed signaling and assess SI/PI across interposer, substrate and PCB.
• Collaborate with layout teams and system partners to resolve complex technical issues.
• Lead and participate in chip architecture discussions and high-performance ASIC design reviews.
• Mentor the SI team and promote design reviews and continuous improvement.

Skills

High-speed signaling

56G PAM4

SerDes architectures

Electromagnetics understanding

Spice simulation

Education

Bachelor's degree in Electrical Engineering

12+ years relevant experience or 8+ with MS or 5+ with PhD

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Job description

Cisco Silicon One seeks a Signal and Power Integrity Technical Leader to guide ASIC packaging development and lead the SI team in defining, designing and verifying packaging for high-volume Cisco platforms.

You will develop rules for ultra-high-speed signaling, ensure power/performance targets, and collaborate with layout and system partners to resolve complex issues while mentoring junior engineers and driving continuous process improvements.