Lead Signal & Power Integrity Architect (Remote)

Cisco Systems, Inc; San Jose (CA); Remote; USD 214,000 - 310,000; Full time

Benefits offered by this job

401(k) matching

Paid parental leave

Health, dental and vision insurance

Sick time off

Job summary

Cisco Silicon One is seeking a seasoned Signal and Power Integrity Technical Leader to guide the packaging SI/PI team in defining, designing, and validating high-performance ASIC packages. You will partner with layout and system teams to ensure optimal SI/PI across interposer, substrate, and PCB while mentoring junior engineers.

The role requires deep expertise in 56G PAM4, high-speed SerDes, and advanced packaging techniques, with a track record of successful tape-outs and strong collaboration

Qualifications

• Bachelor's degree in Electrical Engineering or higher with extensive signal/power integrity focus.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Proficient in high-speed signaling, 56G PAM4+, SerDes architectures, and impedance concepts.
• Hands-on lab experience with SI/PI tools and lab measurement techniques.

Responsibilities

• Lead the Silicon Packaging SI/PI team to define, design and verify ASIC packaging for Cisco platforms.
• Develop and document design rules for ultra-high-speed signaling to meet power/performance/area goals.
• Collaborate with layout, system partners, vendors to resolve complex technical issues.

Skills

Signal integrity

Power integrity

High-speed packaging

Tape-out experience

SerDes design

Channel modeling

BER prediction

Electromagnetics

Team leadership

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

_SPICE_

MATLAB

Python scripting

Job description

Cisco Silicon One is seeking a seasoned Signal and Power Integrity Technical Leader to guide the packaging SI/PI team in defining, designing, and validating high-performance ASIC packages. You will partner with layout and system teams to ensure optimal SI/PI across interposer, substrate, and PCB while mentoring junior engineers.

The role requires deep expertise in 56G PAM4, high-speed SerDes, and advanced packaging techniques, with a track record of successful tape-outs and strong collaboration