Remote ASIC Signal & Power Integrity Lead

Cisco; Bellevue (WA); Hybride; USD 192 000 - 317 000; Plein temps

Résumé du poste

Cisco Silicon One seeks a highly qualified Signal and Power Integrity Technical Leader to guide packaging and SI/PI efforts for next-generation ASICs. Based in San Jose, CA with onsite preference and openness to remote work, you will design, verify, and optimize ultra-high-speed interconnects across interposers, substrates, and PCBs.

You will mentor a multi-disciplinary team, define design rules, collaborate with system partners and vendors, and drive continuous improvements while delivering

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of SI/PI experience or equivalent.
• Experience with multiple high-speed ASIC tape-outs from a packaging perspective.
• Experience with 56G PAM4 and above, high-speed SerDes, channel modeling and electromagnetics.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.

Responsabilités

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power, performance, and area goals.
• Analyze substrate signal integrity (SI) and power integrity (PI) and collaborate with the layout team for optimal interposer, substrate, and PCB solutions.
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
• Collaborate with system partners and vendors to resolve complex technical issues using advanced design rules.
• Lead or participate in chip architecture discussions and mentor the SI team to meet technical specifications.

Connaissances

Signal integrity

Power integrity

Team leadership

Mentoring

Formation

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Outils

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

Description du poste

Cisco Silicon One seeks a highly qualified Signal and Power Integrity Technical Leader to guide packaging and SI/PI efforts for next-generation ASICs. Based in San Jose, CA with onsite preference and openness to remote work, you will design, verify, and optimize ultra-high-speed interconnects across interposers, substrates, and PCBs.

You will mentor a multi-disciplinary team, define design rules, collaborate with system partners and vendors, and drive continuous improvements while delivering