Senior SI/PI Packaging Lead for High-Speed ASICs

Cisco Systems, Inc; San Jose (CA); Hybrid; USD 187,000 - 268,000; Full time

Job summary

Cisco Silicon One in San Jose, CA seeks a highly skilled Signal and Power Integrity Technical Lead to drive the next generation ASIC packaging strategy. You will define, design and verify packaging for high-performance Cisco platforms, guiding SI/PI practices across interposer, substrate, and PCB.

You will mentor junior engineers, lead detailed architectural reviews, and collaborate with cross-functional teams to meet stringent power and signal integrity targets in a fast-paced environment.

Qualifications

• Bachelor's or higher in Electrical Engineering with 8+ years of SI/PI experience, or equivalent.
• Strong knowledge of high-speed signaling theory and 56G PAM4 SerDes concepts.
• Experience with pre- and post-layout SI/PI simulations and toolchains.

Responsibilities

• Develop and document design rules for ultra-high-speed signaling ensuring power, performance, and area goals.
• Analyze substrate SI and PI; collaborate with layout to optimize interposer, substrate, and PCB solutions.
• Design and develop ASIC packages for high-volume release including post-layout extraction.
• Collaborate with partners and leads to resolve complex issues using advanced design rules.
• Define processes, methods, and tools for complex ASIC/package developments.
• Lead or participate in chip architecture discussions and high-performance ASIC design reviews.
• Mentor SI team and coordinate with packaging/hardware teams; promote design reviews and continuous improvement.

Skills

High-Speed Design & Theory

SI/PI Simulation Proficiency

Layout Review & Physical Validation

Circuit Analysis

Communication & Mentoring

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

Job description

Cisco Silicon One in San Jose, CA seeks a highly skilled Signal and Power Integrity Technical Lead to drive the next generation ASIC packaging strategy. You will define, design and verify packaging for high-performance Cisco platforms, guiding SI/PI practices across interposer, substrate, and PCB.

You will mentor junior engineers, lead detailed architectural reviews, and collaborate with cross-functional teams to meet stringent power and signal integrity targets in a fast-paced environment.