Senior ASIC Packaging & SI/PI Engineer

Cisco Systems, Inc; San Jose (CA); On-site; USD 155,000 - 223,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) with Cisco matching

Paid parental leave

Vacation and sick time

Job summary

Cisco Silicon One is seeking a qualified Signal and Power Integrity Engineer to help shape next-generation ASIC packaging for Cisco platforms. The role focuses on ultra-high-speed signaling, SI/PI analysis, and collaboration with layout teams to meet tight power, performance, and area goals.

Join a specialized ASIC team delivering cutting-edge interposer and 2.5D packaging technologies, with opportunities to work across TOR, data centers, and service provider networks.

Qualifications

• Bachelor’s degree in Electrical Engineering with 4+ years of SI/PI experience or advanced degrees with related experience.
• Experience with high-speed design principles and 56G PAM4 SerDes architectures.
• Proficiency in pre- and post-layout SI/PI simulations and physical validation.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling to meet power/performance/area goals.
• Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB solutions.
• Design, document, and develop ASIC packages for high-volume release with post-layout extraction.
• Collaborate with system partners to resolve complex technical issues using advanced design rules.
• Work with vendors and design leads to achieve unified power and signal integrity.

Skills

High-Speed Design

SI/PI Simulation

Layout Review

Circuit Analysis

Transmission Line Theory

Education

B.S. in Electrical Engineering

M.S. in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

Job description

Cisco Silicon One is seeking a qualified Signal and Power Integrity Engineer to help shape next-generation ASIC packaging for Cisco platforms. The role focuses on ultra-high-speed signaling, SI/PI analysis, and collaboration with layout teams to meet tight power, performance, and area goals.

Join a specialized ASIC team delivering cutting-edge interposer and 2.5D packaging technologies, with opportunities to work across TOR, data centers, and service provider networks.