SI/PI Technical Lead for High-Speed ASIC Packaging

Cisco Systems; Boston (MA); On-site; USD 214,000 - 310,000; Full time

Job summary

Cisco Systems in the United States is seeking a Senior Signal and Power Integrity Technical Leader to guide the design and verification of high-performance ASIC packaging. You will lead the SI/PI team, define rules for ultra-high-speed signaling, and collaborate across interposer, substrate, and PCB domains.

You will mentor engineers, drive post-layout extraction, and contribute to advanced packaging strategies (2.5D, CoWoS, EMIB).

Qualifications

• Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience or Master's with 8+ years or PhD with 5+ years.
• Experience with multiple high-speed ASIC tape-outs from a package perspective.
• Experience with 56G PAM4 and above, high-speed SerDes architectures, channel modeling, BER prediction, transmission line theory, and electromagnetics.
• Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
• Experience with SPICE.

Responsibilities

• Lead the Silicon Packaging Signal and Power Integrity Team to define, design and verify ASIC packaging for Cisco platforms.
• Develop, document, and implement design rules for ultra-high-speed signaling while satisfying power, performance, and area goals.
• Analyze substrate SI and PI and collaborate with layout to optimize interposer, substrate, and PCB solutions.
• Design, document, and develop ASIC packages for high-volume, high-quality releases, including post-layout extraction and reporting.
• Collaborate with partners, vendors, and leads to resolve complex SI/PI issues using advanced design rules.
• Define processes, methods, and tools for complex ASIC/package developments.
• Contribute to chip architecture discussions and design reviews of high-performance ASICs including IC/analog/mixed-signal circuits.
• Mentor the SI team and influence packaging/hardware teams to meet specifications and drive innovation.
• Promote design reviews, postmortems, and continuous improvement across multi-disciplinary teams.

Skills

Signal integrity

Power integrity

High-speed ASICs

Tape-outs

SPICE

Lab tools

Python scripting

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Keysight ADS

Ansys HFSS/EM flow

Cadence APD

SPICE

MATLAB

Python

Job description

Cisco Systems in the United States is seeking a Senior Signal and Power Integrity Technical Leader to guide the design and verification of high-performance ASIC packaging. You will lead the SI/PI team, define rules for ultra-high-speed signaling, and collaborate across interposer, substrate, and PCB domains.

You will mentor engineers, drive post-layout extraction, and contribute to advanced packaging strategies (2.5D, CoWoS, EMIB).