Senior SI/PI Packaging Lead for 2.5D ASICs

Cisco Systems, Inc; San Jose (CA); Remote; USD 193,000 - 261,000; Full time

Job summary

Cisco Silicon One is seeking a Signal and Power Integrity Technical Lead to advance next-generation ASIC packaging and high-speed signaling. You will define rules, perform SI/PI analyses, and collaborate with cross-functional teams to ensure power, performance, and area goals are met.

The role requires extensive experience in SI/PI, layout validation, and high-speed memory interfaces, with mentoring responsibilities for junior engineers and a drive for design excellence at scale.

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years of experience, or Master’s with 6+ years, or PhD with 3+ years in SI/PI.
• Experience with high-speed design principles and 56G PAM4 SerDes architectures.
• Proficiency with pre- and post-layout SI/PI simulations using industry tools.
• Experience with layout reviews and physical validation to ensure signal performance and crosstalk mitigation.
• Circuit analysis experience using SPICE for modeling and validation.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling.
• Analyze substrate SI/PI and provide feedback to layout team for optimal solutions.
• Design, document, and develop ASIC packages including post-layout extraction and reporting.
• Collaborate with system partners, vendors, and leads to resolve complex technical issues.
• Define processes, methods, and tools for complex ASIC/package developments.
• Lead or participate in chip architecture discussions for high-performance ASICs.
• Mentor signal integrity team and influence packaging/hardware teams.
• Promote design reviews, postmortems, and continuous improvement across teams.

Skills

High-Speed Design

SI/PI Simulation

Layout Review

SPICE Analysis

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Job description

Cisco Silicon One is seeking a Signal and Power Integrity Technical Lead to advance next-generation ASIC packaging and high-speed signaling. You will define rules, perform SI/PI analyses, and collaborate with cross-functional teams to ensure power, performance, and area goals are met.

The role requires extensive experience in SI/PI, layout validation, and high-speed memory interfaces, with mentoring responsibilities for junior engineers and a drive for design excellence at scale.