Lead, High-Speed ASIC Packaging & SI/PI Design

020 Cisco Systems, Inc.; San Jose (CA); Remote; USD 187,000 - 268,000; Full time

Job summary

Cisco Silicon One in California is seeking a Signal and Power Integrity Technical Lead to define, design, and verify ASIC packaging for high-performance platforms. You will develop design rules for ultra-high-speed signaling, assess SI/PI, and guide layout teams to optimize interposers, substrates, and PCBs.

You’ll lead architecture discussions, mentor junior engineers, and drive post-layout extraction and reporting to meet tight performance and reliability targets.

Qualifications

• Bachelor's degree in Electrical Engineering (or higher)
• 8+ years of relevant signal and power integrity experience, or 6+ years with a Master’s, or 3+ years with a PhD
• Experience with high-speed design principles, including 56G PAM4 SerDes, channel modeling, and BER prediction
• Experience with SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS
• Experience with layout reviews and physical validation using Cadence APD and Ansys EM flows

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling, meeting power, performance, and area goals
• Analyze substrate signal integrity (SI) and power integrity (PI) and collaborate with the layout team
• Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting
• Collaborate with system partners, vendors, and design leads to resolve complex technical issues using advanced technology design rules
• Define processes, methods, and tools for complex ASIC/package developments
• Lead or participate in chip architecture discussions and design reviews of high-performance ASICs
• Mentor and support the SI team and multi-disciplinary packaging groups
• Promote design reviews, postmortems, and continuous improvement across teams

Skills

High-Speed Design

SI/PI Simulation

Layout Review

Circuit Analysis

Transmission Line Theory

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

Job description

Cisco Silicon One in California is seeking a Signal and Power Integrity Technical Lead to define, design, and verify ASIC packaging for high-performance platforms. You will develop design rules for ultra-high-speed signaling, assess SI/PI, and guide layout teams to optimize interposers, substrates, and PCBs.

You’ll lead architecture discussions, mentor junior engineers, and drive post-layout extraction and reporting to meet tight performance and reliability targets.