SI/PI Packaging Engineer for AI & HPC Chips (2.5D/3D)

Meta Careers; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 300,000; Full time

Job summary

Meta Careers in Sunnyvale, CA seeks a highly skilled Silicon Packaging Engineer to own chip-package-system co-design for next-generation AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation in 2.5D/3D packages, collaborating with ASIC, package, PCB, and foundry partners to ensure robust performance and reliability before tape-out.

The role emphasizes channel design, power delivery networks, and reusable SI/PI methodologies across

Responsibilities

• Chip-Package-System Co-Design: drive SI/PI requirements into product definition and net topology.
• Die-Package-Board Co-Optimization: converge bump assignment and stack-up decisions across chiplets.
• Package SI/PI Ownership: lead substrate/interposer stack-up, material selection, reviews, and sign-off.
• High-Speed Interfaces: design margins for PCIe Gen5/Gen6, HBM/HBM4/UHBM, UCIe and other die-to-die links.
• Power Delivery and PDN: analyze AC+DC, impedance targeting, decoupling, IR drop, and di/dt noise.
• Simulation Flow: lead pre-layout and post-layout SI/PI simulations and model development.

Skills

SI/PI Engineering

2.5D/3D Packaging

HBM/UHBM Interfaces

PDN Analysis

Pre/Post-Layout Simulation

Job description

Meta Careers in Sunnyvale, CA seeks a highly skilled Silicon Packaging Engineer to own chip-package-system co-design for next-generation AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation in 2.5D/3D packages, collaborating with ASIC, package, PCB, and foundry partners to ensure robust performance and reliability before tape-out.

The role emphasizes channel design, power delivery networks, and reusable SI/PI methodologies across