Senior SI/PI Engineer for 2.5D/3D Chip-Package Systems

Meta; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Meta is seeking a seasoned Signal Integrity and Power Integrity engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packaging, coordinating with ASIC, package, PCB, and foundry partners to ensure reliable high-speed interfaces and power delivery.

The role involves leading pre/post-layout simulations, modeling, and methodology development to meet strict performance and

Qualifications

• Bachelor's degree or higher in a technical field or equivalent practical experience.
• 8+ years of signal integrity analysis, simulation, and measurement.
• Proficiency with HFSS, Sigrity, Hspice or equivalent tools.
• Experience with 2.5D/3D package design and SIPI concepts.
• Expertise in SDI/PI for high-speed interconnects (HBM, PCIe, SerDes).
• Familiarity with post-Si test for memory interfaces and SERDES.
• Strong collaboration with cross-functional teams across architecture, design, and packaging.

Responsibilities

• Drive SI/PI requirements from architecture through post-silicon validation.
• Lead chip-package-system co-design for 2.5D/3D HPC/AI silicon.
• Converge bump assignment, routing, and stack-up decisions across interfaces.
• Own PDN and impedance budgets across silicon, package, and board.
• Develop SI/PI methods, models, and validation plans.
• Coordinate with foundries/OSATs on interconnect and die-stacking standards.
• Guide cross-functional teams to ensure performance targets pre-tape-out.

Skills

Chip-Package-System Co-Design

SI/PI analysis

High-speed interfaces

Pre/post-layout simulation

Impedance control

Voltage-budget design

Materials selection

Noise/budget analysis

Problem solving & debugging

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in Electrical Engineering, Physics, Mathematics

Tools

Cadence Sigrity

PowerSI

Ansys SIwave

Keysight ADS

HFSS

Job description

Meta is seeking a seasoned Signal Integrity and Power Integrity engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packaging, coordinating with ASIC, package, PCB, and foundry partners to ensure reliable high-speed interfaces and power delivery.

The role involves leading pre/post-layout simulations, modeling, and methodology development to meet strict performance and