Chip Package Designer for 2.5D/3.5D HPC Packaging

Google; Town of Montana (WI); Presencial; USD 163.000 - 236.000; Jornada completa

Descripción de la vacante

Google in Sunnyvale, CA, is seeking a Package Design Engineer (Mid) to develop 2.5D/3.5D package substrates for ML chips. You will collaborate with SI/PI, thermal, mechanical, assembly, and PCB teams to optimize electrical performance and reliability.

You will manage routing feasibility, test vehicles, and design reviews, driving production sign-off and documentation to enable scalable, high-performance hardware deployments.

Formación

• Bachelor's degree or higher in a related engineering field.
• 8 years of chip package substrate design experience with Cadence APD or Mentor Expedition.
• Experience in layout, verification, DFM and production taping.
• Experience in design automation and scripting.

Responsabilidades

• Develop physical package substrate designs for large form-factor ML HPCs.
• Define CAD flow and methodologies to boost productivity in substrate design.
• Drive co-design across chip, package and system levels with sign-off for production.
• Collaborate with SI/PI, thermal and mechanical teams to optimize designs and test vehicles.
• Document requirements and BOM for package substrates.

Conocimientos

Cadence APD

Mentor Expedition

Package design

Design verification

Scripting

Educación

Bachelor's degree in Engineering or related field

Descripción del empleo

Google in Sunnyvale, CA, is seeking a Package Design Engineer (Mid) to develop 2.5D/3.5D package substrates for ML chips. You will collaborate with SI/PI, thermal, mechanical, assembly, and PCB teams to optimize electrical performance and reliability.

You will manage routing feasibility, test vehicles, and design reviews, driving production sign-off and documentation to enable scalable, high-performance hardware deployments.