Senior ASIC Package SI/PI Engineer for AI/HPC

Slope; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

OpenAI is seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for AI/HPC silicon and package design.

The role emphasizes high-speed SerDes, 2.5D/3D packaging SI/PI, and translating simulation results into practical design requirements, closely collaborating with ASIC, package, system, mechanical, thermal, power, and silicon validation teams.

Qualifications

• 5+ years of experience in signal integrity and power integrity.
• Strong fundamentals in transmission-line behavior, impedance, loss, crosstalk, return paths, PDN.
• Hands-on experience with SI/PI simulation tools.
• Experience with package layout environments and SI/PI optimization.
• Ability to collaborate across ASIC, package, PCB, system, and manufacturing teams.

Responsibilities

• Own SI/PI architecture and analysis for advanced AI ASIC packages.
• Develop and optimize high-speed channels for 200G/400G SerDes, PCIe, HBM, DDR.
• Model package, interposer and substrate using 2D/3D EM solvers.
• Define and optimize package stack-ups, transmission lines, vias and return paths.
• Translate channel results into actionable layout guidelines.
• Drive die/package co-design including bump/BGA allocation and routing.
• Develop automation flows for architecture exploration and SI/PI sign-off.

Skills

Signal integrity

Power integrity

High-speed interconnect design

PDN design

Package electrical design

Electromagnetic simulation

Cross-team collaboration

Automation for design flows

Tools

Synopsys HSPICE

Ansys HFSS-PI

SIwave

Cadence Clarity

Sigrity PowerSI/PowerDC

Cadence APD/SIP

2D/3D EM solvers

Job description

OpenAI is seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for AI/HPC silicon and package design.

The role emphasizes high-speed SerDes, 2.5D/3D packaging SI/PI, and translating simulation results into practical design requirements, closely collaborating with ASIC, package, system, mechanical, thermal, power, and silicon validation teams.