Senior Silicon Packaging & SI/PI Engineer

Meta; Menlo Park (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta seeks an experienced Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packages with ASIC, package, PCB, and OSAT partners.

Responsibilities include leading DPCO, substrate/interposer decisions, and validation of high-speed interfaces (HBM, PCIe, SerDes).

Qualifications

• 8+ years of SI/PI analysis, simulation, and measurement.
• Proficient with HFSS, Sigrity, Hspice or similar tools.
• Impedance control and PDN characterization knowledge.
• Experience with 2.5D/3D packaging concepts.
• Expertise in high-speed interconnects (HBM, D2D, PCIe, Ethernet).
• Familiarity with memory, SIPI models and timing budgets.
• Package-level SI/PI across silicon, package, and board.

Responsibilities

• Lead chip-package-system co-design for HPC and AI silicon.
• Drive SI/PI requirements from architecture to post-silicon validation.
• Own substrate/interposer stack-up and material selection.
• Define high-speed interface channels and PDN analysis.
• Develop SI/PI methodology and validate with tests.

Skills

SI/PI experience

HFSS

Sigrity

Hspice

2.5D/3D packaging

HBM

PCIe/SerDes

Power integrity

Tools

Cadence Sigrity

PowerSI

Ansys SIwave

Keysight ADS

Ansys HFSS

Job description

Meta seeks an experienced Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packages with ASIC, package, PCB, and OSAT partners.

Responsibilities include leading DPCO, substrate/interposer decisions, and validation of high-speed interfaces (HBM, PCIe, SerDes).