Chip Package SI/PI Engineer for 2.5D/3D AI Hardware

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking a Chip Package SI/PI Engineer to shape AI/ML hardware acceleration and TPU integration. You will verify complex digital designs focusing on TPU architecture within AI/ML systems and collaborate across design, packaging, and validation teams to meet electrical requirements.

You will be responsible for chip-package-system co-design, SI/PI simulations, and driving packaging implementations from concept to production, contributing to Google's data centers that power millions of

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS or related field.
• 10 years of experience with SI/PI design for chip/package or system PCB.
• Experience with SIPI modeling tool chains (HFSS, ADS, Sigrity, Siwave).

Responsibilities

• Drive chip-package-system co-design with SI/PI analysis and optimization for HPC based on 2.5D/3D package tech.
• Develop Power integrity methodology for advanced package technology.
• Evaluate new package technology and High speed Interface IP.
• Collaborate with multiple teams to drive chip package SI/PI design targets and trade-offs.
• Provide feedback on chip floorplan considering package/system routability and SI/PI.

Skills

SI/PI design

SIPI modeling

Cross-functional collaboration

Education

Bachelor's degree or equivalent practical experience

Tools

HFSS

ADS

Sigrity

Siwave

Job description

Google is seeking a Chip Package SI/PI Engineer to shape AI/ML hardware acceleration and TPU integration. You will verify complex digital designs focusing on TPU architecture within AI/ML systems and collaborate across design, packaging, and validation teams to meet electrical requirements.

You will be responsible for chip-package-system co-design, SI/PI simulations, and driving packaging implementations from concept to production, contributing to Google's data centers that power millions of