SI/PI Engineer – 2.5D/3D Packaging for AI Chips

Amazon; Austin (TX); On-site; USD 136,000 - 184,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs, an organization within Amazon, seeks a Signal & Power Integrity Engineer to join the hardware team and advance SI/PI analysis for next‑generation AI silicon packaging. You will contribute to simulations, modeling, and design decisions across IC, package, and board interfaces.

You will work with senior engineers to meet performance, power delivery, and manufacturing targets, focusing on package‑level SI/PI and co‑design across multi‑chip packaging environments.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years in signal integrity, power integrity, or package design.
• Solid understanding of SI or PI with working awareness of the other.
• Experience with EM simulation and SI/PI tools.
• Understanding of advanced packaging technologies like 2.5D/3D‑IC and RDL.

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and interposer architectures.
• Support package stack‑up design and impedance control analysis.
• Run high-speed channel simulations and analyze PDN performance.
• Model and validate decoupling technologies as needed.
• Coordinate with SoC die-level and board design teams for co-optimization.

Skills

Signal integrity

Power integrity

Package design

Communication

EM simulation

Education

Bachelor's degree in Electrical Engineering

Master’s degree (preferred)

Tools

HFSS

Cadence Sigrity PowerSI/PowerDC/Clarity

ADS

Job description

Annapurna Labs, an organization within Amazon, seeks a Signal & Power Integrity Engineer to join the hardware team and advance SI/PI analysis for next‑generation AI silicon packaging. You will contribute to simulations, modeling, and design decisions across IC, package, and board interfaces.

You will work with senior engineers to meet performance, power delivery, and manufacturing targets, focusing on package‑level SI/PI and co‑design across multi‑chip packaging environments.