Silicon Packaging Engineer (SIPI)

Meta Careers; Sunnyvale, Northern (CA, KY); Hybrid; USD 180,000 - 300,000; Full time

Job summary

Meta Careers in Sunnyvale, CA seeks a highly skilled Silicon Packaging Engineer to own chip-package-system co-design for next-generation AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation in 2.5D/3D packages, collaborating with ASIC, package, PCB, and foundry partners to ensure robust performance and reliability before tape-out.

The role emphasizes channel design, power delivery networks, and reusable SI/PI methodologies across

Responsibilities

• Chip-Package-System Co-Design: drive SI/PI requirements into product definition and net topology.
• Die-Package-Board Co-Optimization: converge bump assignment and stack-up decisions across chiplets.
• Package SI/PI Ownership: lead substrate/interposer stack-up, material selection, reviews, and sign-off.
• High-Speed Interfaces: design margins for PCIe Gen5/Gen6, HBM/HBM4/UHBM, UCIe and other die-to-die links.
• Power Delivery and PDN: analyze AC+DC, impedance targeting, decoupling, IR drop, and di/dt noise.
• Simulation Flow: lead pre-layout and post-layout SI/PI simulations and model development.

Skills

SI/PI Engineering

2.5D/3D Packaging

HBM/UHBM Interfaces

PDN Analysis

Pre/Post-Layout Simulation

Job description

# Silicon Packaging Engineer (SIPI)Sunnyvale, CA+1 locationEngineering+ 3 moreApply nowWe are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing silicon. In this role you will drive SI/PI requirements from architecture definition through post-silicon validation across 2.5D/3D heterogeneous packages — silicon interposer, RDL fan-out, wafer-on-wafer die stacking, and high-density organic substrates. You will work closely with ASIC architecture, physical design, package layout, PCB, and foundry/OSAT partners to ensure high-speed interfaces and power delivery networks meet performance, margin, and reliability targets before tape-out and Gerber release.---## Silicon Packaging Engineer (SIPI) Responsibilities* Chip-Package-System Co-Design: Drive SI/PI requirements analysis and optimization into product definition — chip floorplan, bump map, power tree structure, and net topology — for HPC and AI silicon built on 2.5D/3D package technology.* Die-Package-Board Co-Optimization (DPCO): Partner with package layout and physical design to converge bump assignment, escape routing, and stack-up decisions across multiple disparate chiplets.* Package SI/PI Ownership: Lead ASIC package SI/PI design activities including substrate and interposer stack-up and material selection, design guide authoring, layout review, and post-layout sign-off.* High-Speed Interfaces: Own channel design and margining for HBM/HBM4/UHBM, UCIe and other die-to-die links, PCIe Gen 5/Gen 6, Ethernet SerDes, and next-generation memory interfaces.* Power Delivery: Execute package and board PDN AC+DC analysis for low-voltage/high-current supplies, including impedance targeting, decoupling optimization, IR drop, and di/dt noise.* Simulation Flow: Lead pre-layout and post-layout simulation flows for high-speed I/O and PDN; build simulation models and develop reusable SI/PI methodology.