Senior Wireless SOC Verification Engineer

Apple Inc.; Sunnyvale (CA); On-site; USD 175,000 - 308,500; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Sunnyvale, CA, is seeking a Design Verification Engineer to verify complex Wireless SOCs. You will craft reusable UVM test benches and integrate multiple VIPs for PCIe, memory subsystems, and power-management components.

You’ll collaborate across DV teams, translate specifications into coverage-driven plans, and drive tape-out readiness in a fast-paced silicon environment. Strong SystemVerilog and UVM skills are required.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage closure.
• Expertise in SystemVerilog coding and UVM methodology.

Responsibilities

• Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as PCIE, CPUs and multi-processor systems, Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes.
• Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF simulations.
• Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
• Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level.
• Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design.
• Work closely with DV methodology architects to improve verification metrics.

Skills

SystemVerilog

UVM methodology

ASIC & SOC DV

PCIe verification

Low Power verification

Bus fabric verification

Education

BS degree in Electrical Engineering

Tools

UPF

Formal Verification tools

Job description

Apple Inc. in Sunnyvale, CA, is seeking a Design Verification Engineer to verify complex Wireless SOCs. You will craft reusable UVM test benches and integrate multiple VIPs for PCIe, memory subsystems, and power-management components.

You’ll collaborate across DV teams, translate specifications into coverage-driven plans, and drive tape-out readiness in a fast-paced silicon environment. Strong SystemVerilog and UVM skills are required.