Cellular SoC Verification Engineer — Innovate & Verify

Apple Inc.; Sunnyvale (CA); In loco; USD 129.000 - 195.000; Tempo pieno

Vantaggi offerti da questo lavoro

Stock options

Education reimbursement

Benefits package

Descrizione del lavoro

Apple Inc. in Sunnyvale, CA invites a Design Verification Engineer to join the silicon design group responsible for Cellular SoCs. You will verify large-scale SOCs, develop reusable UVM-based test benches, and drive coverage-driven verification to ensure right-first-time chips.

BS required; strong SystemVerilog, Python, C++, or Java skills; MS preferred. We offer stock programs, education reimbursement, comprehensive benefits, and competitive base pay.

Competenze

• BS is required.
• Programming experience in SystemVerilog, Python, C++ or Java.

Mansioni

• Learn all aspects of a large scale SOC design and verification.
• Develop sophisticated DV environments and reusable UVM test benches.
• Deliver proof of right-first-time silicon through coverage-driven testing.

Conoscenze

SystemVerilog

Python

C++

Java

Formazione

Bachelor's degree in EE or CS

MS in EE or CS preferred

Descrizione del lavoro

Apple Inc. in Sunnyvale, CA invites a Design Verification Engineer to join the silicon design group responsible for Cellular SoCs. You will verify large-scale SOCs, develop reusable UVM-based test benches, and drive coverage-driven verification to ensure right-first-time chips.

BS required; strong SystemVerilog, Python, C++, or Java skills; MS preferred. We offer stock programs, education reimbursement, comprehensive benefits, and competitive base pay.