SoC DV Engineer - Verilog, UVM & Testbench Expert

Apple Inc.; Cupertino (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs.

You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/SystemVerilog, digital design fundamentals, and scripting (Python/Perl).

Qualifications

• BS + 3 years of relevant industry experience.
• Strong knowledge of Verilog/SystemVerilog and digital design.
• Experience with test benches, coverage, and UVM is desirable.

Responsibilities

• Verify functionality and performance of Apple’s SOCs and IPs.
• Develop and execute test plans, coverage plans, and verification methodologies.
• Run regressions, triage bugs, and analyze coverage to drive top results.

Skills

Verilog/SystemVerilog

C/C++

Digital design fundamentals

Python/Perl scripting

Independent work

Education

BS + 3 years experience

Job description

Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs.

You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/SystemVerilog, digital design fundamentals, and scripting (Python/Perl).