Design Verification Engineer (VLSI/UVM)

Apple Inc.; Waltham (MA); On-site; USD 124,000 - 175,000; Full time

Benefits offered by this job

Stock options eligibility

Educational reimbursement

Comprehensive health coverage

Relocation assistance

Job summary

Apple Inc. in Waltham, MA seeks a verification engineer to design and execute detailed test plans for high‑performance VLSI blocks. You will create verification environments with stimulus, checkers, and coverage, and run regression suites across IP and SoC levels.

You will use SystemVerilog and UVM to build testbenches, automate tasks with Python/Perl/Tcl, and leverage formal verification tools and industry-standard tools such as Cadence Xcelium, Verdi, Jasper Gold, and VManager.

Qualifications

• Master’s degree or foreign equivalent in Computer Engineering or related field.
• Experience and/or education must include: Developing detailed test plans from design specifications
• Experience with SystemVerilog to verify high performance VLSI designs
• Experience with UVM to develop testbenches, tests, sequences, scoreboards, assertions, and coverage objects
• Setting up and executing regression suites
• Root-cause debugging of regression failures; Analyzing functional and code coverage reports and closing coverage gaps
• Using Python, Perl, or Tcl to automate tasks
• Utilization of formal verification tools

Responsibilities

• Develop detailed test plans from design specifications.
• Build verification environments including stimulus, checkers, assertions, trackers, and coverage.
• Execute verification plans across DV bring-up, regression, and debugging.
• Develop block/IP/SoC level test-benches and track DV progress using metrics.

Skills

Test planning

Regression debugging

Testbench development

Coverage analysis

Root-cause analysis

Education

Master’s degree in Computer Engineering or related field

Tools

SystemVerilog

UVM

Python

Perl

Tcl

Formal verification tools

Cadence Xcelium

VManager

Virtuoso

Jasper Gold

Verdi

Job description

Apple Inc. in Waltham, MA seeks a verification engineer to design and execute detailed test plans for high‑performance VLSI blocks. You will create verification environments with stimulus, checkers, and coverage, and run regression suites across IP and SoC levels.

You will use SystemVerilog and UVM to build testbenches, automate tasks with Python/Perl/Tcl, and leverage formal verification tools and industry-standard tools such as Cadence Xcelium, Verdi, Jasper Gold, and VManager.