Senior Video Codec ASIC Design Engineer

ByteDance; San Jose (CA); On-site; USD 218,000 - 480,000; Full time

Benefits offered by this job

Health insurance

401(k) plan with company match

Paid parental leave

Disability coverage

Life insurance

Wellbeing benefits

Paid holidays

Paid sick days

Paid Personal Time

Job summary

ByteDance is seeking an ASIC Design Engineer for the Video Silicon IP team to build high performance video codec hardware (FPGA/ASIC). The role involves RTL design, architecture collaboration, and verification to deliver scalable video processing IPs.

You will work with architecture, algorithm, software, firmware and hardware teams to translate codec standards into efficient hardware implementations and meet strict area and power targets.

Qualifications

• MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.

Responsibilities

• Design RTL for video codec pipelines including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS) and in-loop filters.
• Collaborate with architecture, algorithm and verification teams to build high performance, low power video processing IPs.
• Develop micro-architectures to meet area, power, and performance targets for multi-standard codec cores.
• Translate codec specs into implementable hardware architectures with algorithm teams.
• Drive functional correctness with verification using UVM test benches and close RTL coverage metrics.
• Coordinate with synthesis, timing analysis, and physical design for timing closure.

Skills

SystemVerilog RTL

C++

Python

Digital design

VLSI concepts

Education

MS/PhD in Electrical Engineering or related field

Tools

UVM

DPI

Job description

ByteDance is seeking an ASIC Design Engineer for the Video Silicon IP team to build high performance video codec hardware (FPGA/ASIC). The role involves RTL design, architecture collaboration, and verification to deliver scalable video processing IPs.

You will work with architecture, algorithm, software, firmware and hardware teams to translate codec standards into efficient hardware implementations and meet strict area and power targets.