Senior ASIC Design Engineer: Video Codec & RTL Expert

Bytedance; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

ByteDance is seeking an experienced ASIC Design Engineer for the Video Silicon IP team in San Jose. You will drive RTL ownership and work with architecture, algorithm and verification teams to build high-performance video processing IPs.

Responsibilities include designing RTL for multi-standard codecs, optimizing for area and power, and ensuring timing closure with synthesis and CDC checks. External collaboration will translate codec specs into hardware architectures.

Qualifications

• MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
• Scripting proficiency in Python for EDA flow automation.

Responsibilities

• As an ASIC Design Engineer, work with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Apply knowledge of computer architecture and ASIC design to create ASIC design for compressing and processing still images and videos.
• Develop micro-architectures to meet area, power, and performance targets for multi-standard codec cores.
• Collaborate with algorithm teams to translate codec specs into hardware architectures.
• Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages.
• Drive functional correctness with the verification team using UVM test benches; debug RTL coverage metrics.
• Understand synthesis, timing analysis, and CDC/RDC checks; assist floor planning and timing closure.

Skills

SystemVerilog

Python

RTL design

UVM

HLS

Education

MS/PhD in Electrical Engineering

Tools

SystemVerilog

UVM

C++

Python

Job description

ByteDance is seeking an experienced ASIC Design Engineer for the Video Silicon IP team in San Jose. You will drive RTL ownership and work with architecture, algorithm and verification teams to build high-performance video processing IPs.

Responsibilities include designing RTL for multi-standard codecs, optimizing for area and power, and ensuring timing closure with synthesis and CDC checks. External collaboration will translate codec specs into hardware architectures.