Graduate ASIC Design Engineer – Video Codec

ByteDance; San Jose (CA); On-site; USD 128,000 - 317,000; Full time

Job summary

ByteDance in California is seeking an ASIC Design Engineer for the Video Silicon IP team to design high-performance, low-power video processing IPs for encoding and processing. You will collaborate with architecture, algorithm and verification teams, applying computer architecture and ASIC design knowledge to create ASICs for compressing and processing images and video.

Bachelor's degree and hands-on RTL/HLS, UVM, SystemC experience required; prior FPGA/ASIC design exposure and Python scripting

Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering or a related discipline.
• Knowledge of video codecs and media processing.
• Experience with RTL design (SystemVerilog) or high-level synthesis (HLS).
• Experience with UVM, SystemC, or DPI.
• Good programming skills in Python for automation.

Responsibilities

• As an ASIC Design Engineer in the Video Silicon IP team, collaborate with architecture, algorithm and verification teams to build high performance and low power video processing IPs; apply ASIC design to create IPs for compressing and processing still images and videos.

Skills

Video codec knowledge

RTL design (SystemVerilog) or HLS

UVM methodology

SystemC or DPI

Python

FPGA/ASIC design experience

Education

Bachelor's degree in Computer Science, Electrical Engineering or related discipline

Job description

ByteDance in California is seeking an ASIC Design Engineer for the Video Silicon IP team to design high-performance, low-power video processing IPs for encoding and processing. You will collaborate with architecture, algorithm and verification teams, applying computer architecture and ASIC design knowledge to create ASICs for compressing and processing images and video.

Bachelor's degree and hands-on RTL/HLS, UVM, SystemC experience required; prior FPGA/ASIC design exposure and Python scripting