Video Codec ASIC Verification Engineer

ByteDance

San Jose (CA)

On-site

USD 218,000 - 480,000

Full time

32 hours ago

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Benefits offered by this job

Medical insurance

Dental & Vision insurance

401(k) with company match

Paid parental leave

Disability coverage

Life insurance

Wellbeing benefits

10 paid holidays per year

10 paid sick days per year

Paid Personal Time

Job summary

ByteDance’s team in California is seeking a design verification engineer to help deliver a Video Codec IP for FPGA/ASIC platforms. You will generate test benches, run simulations, and debug TB/Design issues with a collaborative team of architects, FPGA/ASIC designers, and verification experts.

The role emphasizes hands-on regression testing, test plan creation, bug tracking leadership, and waveform analysis using VCS and Verdi to ensure high quality, scalable video processing engines within a

Qualifications

Experience with SystemVerilog and UVM methodologies.
Knowledge of SystemC and DPI.
Excellent scripting skills in Perl, Python, Tcl, and Unix-shell.
Experience generating test benches and leading bug tracking.
Hands-on waveform debug with TB/Design isolation using VCS/Verdi.

Responsibilities

In this role, you will generate test benches and run simulations to deliver a Video Codec IP.
You will work with architects and design engineers to develop test plans, lead bug tracking, and automate regression testing.