Video Silicon IP ASIC Design Engineer

ByteDance; San Jose (CA); On-site; USD 162,000 - 317,000; Full time

Job summary

ByteDance is seeking an ASIC Design Engineer for the Video Silicon IP team to design high-performance video codec hardware (FPGA/ASIC). You will work with architecture, algorithm, software and verification peers to deliver scalable video processing IPs and meet strict PPA targets across multi-standard codecs.

The role requires SystemVerilog/Verilog RTL design, RTL ownership, and collaboration to translate codec specs into efficient hardware architectures; familiarity with UVM/DPI/C++ is a plus.

Qualifications

• MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
• 2 years of ASIC front-end design experience as a primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM/DPI/C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, bus interfaces (AXI/APB), and SV assertion basics.
• Scripting proficiency in Python for EDA flow automation.

Responsibilities

• Collaborate with architecture, algorithm and verification teams to build high performance and low power video processing IPs.
• Design RTL for video codec pipeline stages including intra/inter prediction, transform, quantization, entropy coding and in-loop filters.
• Drive functional correctness with the verification team using UVM test benches and close RTL coverage metrics.
• Understand synthesis, timing analysis and CDC/RDC checks; coordinate with physical design for timing closure.

Skills

Python scripting

UVM familiarity

C++ familiarity

Education

MS/PhD in Electrical/Computer Engineering

Tools

SystemVerilog RTL design

High Level Synthesis (HLS)

UVM

Job description

ByteDance is seeking an ASIC Design Engineer for the Video Silicon IP team to design high-performance video codec hardware (FPGA/ASIC). You will work with architecture, algorithm, software and verification peers to deliver scalable video processing IPs and meet strict PPA targets across multi-standard codecs.

The role requires SystemVerilog/Verilog RTL design, RTL ownership, and collaboration to translate codec specs into efficient hardware architectures; familiarity with UVM/DPI/C++ is a plus.