Senior Verification Engineer, SoC & IP (SV/UVM)

Apple, Inc.; Waltham (MA); On-site; USD 135,000 - 250,000; Full time

Benefits offered by this job

Health insurance

Retirement benefits

Stock programs

Relocation support

Tuition reimbursement

Employee stock purchase plan

Product discounts

Free services

Job summary

Waltham, Massachusetts-based Apple, Inc. seeks a design verification engineer to craft first silicon for IP designs and establish pre-silicon DV methodology.

You will develop verification environments with stimulus, checkers, and coverage, and drive RTL sign-off readiness with a focus on efficiency using LLMs. The role requires SystemVerilog/UVM expertise, scalable test benches, and collaboration across IP/SoC teams.

Qualifications

• BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Skills

SystemVerilog

UVM

OOP

LLMs for verification

Power-aware UPF

Education

BS degree in technical subject area

MS degree in a technical subject area

Tools

Python/Perl/TCL scripting

Job description

Waltham, Massachusetts-based Apple, Inc. seeks a design verification engineer to craft first silicon for IP designs and establish pre-silicon DV methodology.

You will develop verification environments with stimulus, checkers, and coverage, and drive RTL sign-off readiness with a focus on efficiency using LLMs. The role requires SystemVerilog/UVM expertise, scalable test benches, and collaboration across IP/SoC teams.