Senior Design Verification Engineer – SoC & UVM Expert

Apple Inc.; Cary (NC); Sur place; USD 150 000 - 200 000; Plein temps

Résumé du poste

Apple Inc. is seeking a Design Verification (DV) Engineer to drive pre-silicon verification for IP and SoC designs. You will establish DV methodologies, build verification environments with stimulus and checkers, and develop robust testbenches to ensure bug-free silicon before tape-out.

The role emphasizes writing tests in SystemVerilog/UVM, debugging regressions, and using LLMs to enhance verification efficiency and quality across IP blocks.

Qualifications

• BS degree in a technical subject and 10 years of relevant industry experience or equivalent.
• Experience developing DV methodologies, test plans and verification environments.
• Proficient in SystemVerilog/UVM testbench development and debugging DV issues.
• Ability to leverage LLMs to improve DV efficiency and quality.

Responsabilités

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Connaissances

SystemVerilog

UVM

OOP concepts

Python scripting

LLMs in verification

UPF power-aware

Testbench design

Verification methodologies

Formation

BS degree in technical subject

Outils

Simulators

Waveform viewers

Scripting: TCL

Emulation

Description du poste

Apple Inc. is seeking a Design Verification (DV) Engineer to drive pre-silicon verification for IP and SoC designs. You will establish DV methodologies, build verification environments with stimulus and checkers, and develop robust testbenches to ensure bug-free silicon before tape-out.

The role emphasizes writing tests in SystemVerilog/UVM, debugging regressions, and using LLMs to enhance verification efficiency and quality across IP blocks.