Senior Design Verification Engineer – SoC Pre-Silicon

Apple Inc.; Beaverton (OR); On-site; USD 150,000 - 210,000; Full time

Job summary

Apple Inc. is seeking an outstanding Design Verification Engineer to enable first silicon for IP designs. You will develop DV methodology, write test plans, and build verification environments in SystemVerilog/UVM to stress the design.

This role focuses on bug-free silicon, regression debugging, and sign-off readiness. Proficiency with LLMs for efficiency and experience in UPF or similar methodologies are advantageous; deep knowledge of OOP, SystemVerilog, and UVM is expected.

Qualifications

• BS degree in a technical subject with 10+ years of relevant industry experience.
• Experience with SystemVerilog/UVM verification is required.
• Strong debugging, regression, and test-plan development skills.

Responsibilities

• Study design specification and create test plan.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Skills

SystemVerilog

UVM

Testbench development

Python

LLMs in verification

UPF / power-aware

Education

BS degree in technical subject

Tools

Waveform viewers

Build & run automation

Simulators

Debugger tools

Job description

Apple Inc. is seeking an outstanding Design Verification Engineer to enable first silicon for IP designs. You will develop DV methodology, write test plans, and build verification environments in SystemVerilog/UVM to stress the design.

This role focuses on bug-free silicon, regression debugging, and sign-off readiness. Proficiency with LLMs for efficiency and experience in UPF or similar methodologies are advantageous; deep knowledge of OOP, SystemVerilog, and UVM is expected.