Senior Design Verification Engineer – SoC First Silicon

Apple Inc.; United States; On-site; USD 140,000 - 230,000; Full time

Job summary

Apple Inc. is seeking an outstanding Design Verification Engineer to help deliver bug-free first silicon for IP designs. You will establish DV methodologies, develop verification environments with stimulus and checkers, and drive test plans through RTL freeze and tape-out.

A strong background in SystemVerilog, UVM, and scalable test-benches is essential. With a BS degree and 10+ years of experience, you will leverage robust scripting skills (Python/Perl/TCL) and experience with PCIe/DDR or

Qualifications

• BS degree in technical subject area with 10+ years of industry experience.
• Strong knowledge of OOP, SystemVerilog and UVM.
• Experience designing scalable, portable test-benches and verification plans.
• Proficient in Python, Perl, and TCL scripting.

Responsibilities

• Define and implement DV methodology and verification environments for pre-silicon IP designs.
• Develop test plans, stimulus, checkers, and coverage to achieve bug-free silicon.
• Write, debug, and maintain test-benches across IP, block, and SoC levels.
• Track and report DV progress using metrics such as bugs and coverage; support RTL freeze and tape-out.
• Leverage LLMs to improve verification efficiency and quality.

Skills

OOP

Test bench design

Verification methodologies

Debugging

Automation scripting

Power-aware verification concepts

Education

BS degree in technical subject area

Tools

SystemVerilog

UVM

Python

Perl

TCL

PCIe

USB

DDR

LLMs

emulation

Job description

Apple Inc. is seeking an outstanding Design Verification Engineer to help deliver bug-free first silicon for IP designs. You will establish DV methodologies, develop verification environments with stimulus and checkers, and drive test plans through RTL freeze and tape-out.

A strong background in SystemVerilog, UVM, and scalable test-benches is essential. With a BS degree and 10+ years of experience, you will leverage robust scripting skills (Python/Perl/TCL) and experience with PCIe/DDR or