Lead Design Verification Engineer, SoC & IP (Pre-Silicon)

Apple, Inc.; San Francisco (CA); Presencial; USD 150.000 - 278.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Comprehensive medical and dental cover

Retirement benefits

Employee stock programs + stock plan

Relocation assistance

Tuition reimbursement

Descripción de la vacante

Apple in the San Francisco Bay Area seeks a design verification engineer to help deliver first silicon for IP designs. You will establish DV methodology, develop verification environments, create stimulus and checkers, and drive tests through RTL freeze and tape-out.

You will build testbenches in SystemVerilog/UVM, debug failures, and measure coverage while leveraging LLMs for efficiency. BS with 3+ years required; MS strongly preferred.

Formación

• BS degree in a technical subject area with 3+ years of relevant industry experience.
• MS degree strongly preferred.
• Strong knowledge of OOP, SystemVerilog and UVM.
• Strong knowledge in developing scalable and portable testbenches.
• Experience with verification methodologies and tools such as simulators, waveform viewer, build/run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Experience with power-aware (UPF) verification.
• Knowledge of scripting languages such as Python, Perl, TCL.
• Some experience with PCIe, USB, or DDR is a plus.
• Knowledge of formal verification is a plus.

Responsabilidades

• Study design specification and create test plan.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Conocimientos

SystemVerilog

UVM

OOP

Educación

BS degree in a technical subject

MS degree preferred

Herramientas

Simulators

Waveform viewer

Build/Run automation

Coverage tools

Gate-level simulations

UPF power-aware verification

Descripción del empleo

Apple in the San Francisco Bay Area seeks a design verification engineer to help deliver first silicon for IP designs. You will establish DV methodology, develop verification environments, create stimulus and checkers, and drive tests through RTL freeze and tape-out.

You will build testbenches in SystemVerilog/UVM, debug failures, and measure coverage while leveraging LLMs for efficiency. BS with 3+ years required; MS strongly preferred.