Senior DV Engineer, SoC/IP (SystemVerilog/UVM)

Apple, Inc.; Cary (NC); On-site; USD 190,000 - 230,000; Full time

Job summary

Apple, Inc. is seeking a design verification engineer to drive pre-silicon validation for IP blocks and full SoC portions. You will define DV methodology, build verification environments with stimulus and checkers, and write tests.

The role emphasizes scalability, regression debugging, and leveraging LLMs to improve quality and speed. The candidate should have a strong background in SystemVerilog/UVM, verification methodologies, and experience with power-aware techniques.

Qualifications

• BS degree in a technical subject or equivalent.
• Deep knowledge of SystemVerilog and UVM.
• Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
• Experience with LLMs for efficiency and quality.
• Knowledge of power-aware (UPF) verification methodology is a plus.
• Scripting in Python, Perl, TCL.
• Experience with PCIe or USB; DDR knowledge is a plus.

Responsibilities

• Study design specification and create test plan.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Skills

SystemVerilog

UVM

OOP concepts

Verification methodologies

LLMs for verification

UPF

Python

Perl

TCL

PCIe

USB

DDR protocols

Emulation

Gate-level simulations

Waveform viewers

Education

BS degree in technical subject

Tools

Simulators

Waveform viewers

Automation tools

Coverage tools

Job description

Apple, Inc. is seeking a design verification engineer to drive pre-silicon validation for IP blocks and full SoC portions. You will define DV methodology, build verification environments with stimulus and checkers, and write tests.

The role emphasizes scalability, regression debugging, and leveraging LLMs to improve quality and speed. The candidate should have a strong background in SystemVerilog/UVM, verification methodologies, and experience with power-aware techniques.