Senior Design Verification Engineer - SoC/IP

Apple, Inc.; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Apple, Inc. is seeking a design verification engineer to enable first silicon for IP designs and to drive pre-silicon verification across DV methodology, test plans, environments, stimulus and checkers.

You will develop verification plans, bring-up DV environments, run regressions, and report DV progress using metrics such as bugs and coverage, while leveraging LLMs to boost efficiency and quality.

Qualifications

• BS degree in a technical subject and minimum 3 years relevant industry experience or equivalent.
• Experience with SystemVerilog/UVM and verification methodologies.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Skills

SystemVerilog

UVM

OOP

Testbenches

Education

Bachelor's degree in a technical field

MS degree in a technical field

Tools

Simulators

Waveform viewer

Automation scripts

Python

Perl

TCL

UPF

PCIe

USB

DDR

Job description

Apple, Inc. is seeking a design verification engineer to enable first silicon for IP designs and to drive pre-silicon verification across DV methodology, test plans, environments, stimulus and checkers.

You will develop verification plans, bring-up DV environments, run regressions, and report DV progress using metrics such as bugs and coverage, while leveraging LLMs to boost efficiency and quality.