Pre-Silicon Digital Verification Engineer (UVM/Formal)

Apple, Inc.; Sunnyvale (CA); On-site; USD 150,000 - 278,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple, Inc. in Sunnyvale, California, is seeking a Pre-Silicon Digital Verification Engineer to join its mixed signal ASIC team.

You will verify complex digital IPs and own verification testbenches using SystemVerilog, UVM, and formal methods, ensuring bug-free designs toward tapeout. You will collaborate with system architects and digital designers to create precise specifications, build verification plans, and develop drivers, tests, and checkers while improving coverage.

Qualifications

• BS and a minimum of 3 years of relevant industry experience.
• Extensive coursework in digital design and computer architecture.
• Foundation in object oriented programming techniques.
• Lab courses or work experience with SystemVerilog.
• Familiar with constrained random verification techniques.
• Familiarity with clock domain crossing design and verification techniques.

Responsibilities

• Collaborate in developing precise design specifications for digital control blocks
• Use design specifications to create block and chip level verification plans
• Architect and create block level verification elements
• Assist in architecting chip and system level verification environments
• Use System Verilog and UVM to develop drivers, tests, reference models and checkers
• Debug test failures and work with designers to develop fixes
• Use functional and code coverage to track progress and gauge tapeout readiness

Skills

Digital design

Computer architecture

Object oriented programming

Education

Bachelor's degree

Tools

SystemVerilog

UVM

Job description

Apple, Inc. in Sunnyvale, California, is seeking a Pre-Silicon Digital Verification Engineer to join its mixed signal ASIC team.

You will verify complex digital IPs and own verification testbenches using SystemVerilog, UVM, and formal methods, ensuring bug-free designs toward tapeout. You will collaborate with system architects and digital designers to create precise specifications, build verification plans, and develop drivers, tests, and checkers while improving coverage.