Senior Substrate & 3DIC Packaging Engineer

TSMC - Taiwan Semiconductor Manufacturing Company Limited; San Jose (CA); On-site; USD 153,500 - 250,000; Full time

Benefits offered by this job

Comprehensive benefits package

Market competitive pay

Extensive development opportunities

Job summary

A leading semiconductor foundry in San Jose seeks a highly skilled Substrate / Advanced Package Engineer to innovate in 3DIC design and packaging. Responsibilities include designing, simulating, and optimizing advanced packaging technologies while collaborating with cross-functional teams. Candidates should have a Master’s degree or Ph.D. in Engineering and over 15 years of relevant experience. The role promises significant impact within a cutting-edge environment focused on technological advancements.

Qualifications

• Minimum 15 years of expertise in substrate design.
• Understanding of semiconductor packaging processes.
• Knowledge of thermal effects in packaging.

Responsibilities

• Design and optimize advanced packaging for 3DIC applications.
• Collaborate to define specifications and requirements.
• Perform modeling of warpage and reliability.

Skills

Expertise in advanced packaging technologies

Strong problem-solving skills

Excellent analytical skills

Strong collaboration skills

Ability to mentor junior engineers

Education

Master’s degree or Ph.D. in Electrical or Mechanical Engineering

Tools

EDA tools

Modeling software

Job description

A leading semiconductor foundry in San Jose seeks a highly skilled Substrate / Advanced Package Engineer to innovate in 3DIC design and packaging. Responsibilities include designing, simulating, and optimizing advanced packaging technologies while collaborating with cross-functional teams. Candidates should have a Master’s degree or Ph.D. in Engineering and over 15 years of relevant experience. The role promises significant impact within a cutting-edge environment focused on technological advancements.