Senior Staff Verification Lead - Cache Interconnect

SwiftCruit; Boston (MA); On-site; USD 140,000 - 210,000; Full time

Job summary

SiFive is seeking a Senior Staff Design Verification Engineer to lead verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. You will define verification strategy, develop environments, and partner with architecture, RTL, and software teams to ensure protocol correctness and QoS across multiple interfaces.

Role emphasizes early risk identification, effective debugging, and building reusable verification infrastructure.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science or a related field.
• 8+ years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role.
• Strong hands-on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.
• Strong understanding of cache-coherent systems, on-chip interconnects, memory subsystem behavior, and verification of ordering and flow-control semantics.
• Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high-performance interconnect standards.
• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
• Strong scripting and automation skills in Python or similar languages.
• Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast-moving environment.

Responsibilities

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior.
• Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows.
• Create high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth-sensitive behavior.
• Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
• Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you.
• Mentor engineers and help raise verification quality across the team.

Skills

SystemVerilog

Verification infrastructure

Python scripting

Inter-team communication

Cache-coherent systems

Interconnect protocols CHI ACE CXL AXI

Test plans and coverage models

Debug and root-cause analysis

Education

BS or MS in Electrical Engineering, Computer Engineering, Computer Science

Tools

Formal verification

Emulation/FPGA debugging

Job description

SiFive is seeking a Senior Staff Design Verification Engineer to lead verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs. You will define verification strategy, develop environments, and partner with architecture, RTL, and software teams to ensure protocol correctness and QoS across multiple interfaces.

Role emphasizes early risk identification, effective debugging, and building reusable verification infrastructure.