Lead Design Verification Architect — Cache Coherence

SiFive; Boston (MA); On-site; USD 231,000 - 283,000; Full time

Job summary

SiFive is seeking a Principal Design Verification Engineer to lead verification strategy and execution for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms. This prime role requires defining architecture-aware verification plans, identifying risks early, and elevating verification quality across architecture, RTL, formal, and performance teams.

You will drive verification across interfaces, bridges, and data-movement paths, develop

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of verification experience in CPU, subsystem, SoC, or ASIC.
• Strong hands-on SystemVerilog-based verification experience for complex subsystems.
• Deep experience verifying cache-coherent interconnects and memory-subsystem behavior.

Responsibilities

• Lead verification planning and execution from block to subsystem integration.
• Define verification strategy, test plans, assertions, scoreboards, and coverage models.
• Drive verification across interfaces, bridges, and protocol adaptation layers.
• Develop directed and constrained-random scenarios to expose corner cases in coherency and QoS.
• Collaborate with architecture, RTL, and formal teams to reduce ambiguity and improve debugability.
• Mentor engineers and elevate verification practices across the organization.

Skills

SystemVerilog

Verification planning

Python scripting

Debugging

Architectural verification

Education

BS/MS/PhD in EE/CE/CS

Tools

UVM

Verdi

Job description

SiFive is seeking a Principal Design Verification Engineer to lead verification strategy and execution for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms. This prime role requires defining architecture-aware verification plans, identifying risks early, and elevating verification quality across architecture, RTL, formal, and performance teams.

You will drive verification across interfaces, bridges, and data-movement paths, develop