Senior Staff Verification Engineer, Coherent Interconnect

SiFive, Inc.; Massachusetts; On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Healthcare benefits

Retirement plans

Paid time off

Job summary

SiFive, Inc. is seeking a Senior Staff Design Verification Engineer to lead the verification of cache-coherent interconnect subsystems. The role focuses on defining strategy, identifying risks, and solving verification challenges in high-performance SoCs.

Applicants should have a strong background in SystemVerilog, ASIC design verification, and must be able to work collaboratively across various teams to drive high technology standards.

This position provides competitive compensation and a comprehensive benefits package.

Qualifications

• 8+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog.
• Excellent understanding of high-performance SoCs.

Responsibilities

• Own verification planning and execution for a scalable cache-coherent interconnect.
• Develop and maintain verification environments and models.
• Mentor engineers to improve verification quality.

Skills

SystemVerilog

Verification infrastructure

Scripting in Python

Cache-coherent systems

High-performance interconnect standards

Education

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Formal verification tools

Debugging tools

Job description

SiFive, Inc. is seeking a Senior Staff Design Verification Engineer to lead the verification of cache-coherent interconnect subsystems. The role focuses on defining strategy, identifying risks, and solving verification challenges in high-performance SoCs.

Applicants should have a strong background in SystemVerilog, ASIC design verification, and must be able to work collaboratively across various teams to drive high technology standards.

This position provides competitive compensation and a comprehensive benefits package.