Staff Design Verification Engineer: Coherent Interconnect

SiFive; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs. You will own complex verification programs spanning data movement, protocol correctness, and subsystem integration across multiple interface types.

This role emphasizes strategy over execution, with collaboration across architecture, design, formal, and software teams to accelerate debug and sign-off.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science
• 7+ years of experience in ASIC or SoC design verification
• Strong hands-on experience with SystemVerilog and UVM-based verification
• Strong understanding of cache-coherent systems and on-chip interconnects
• Experience verifying protocol behavior including ordering, flow control, backpressure
• Experience building reusable testbench components, assertions, coverage models
• Strong debugging skills and ability to root-cause issues across layers

Responsibilities

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration.
• Develop and maintain robust verification environments, checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, and error handling.
• Verify protocol adaptation and integration across multiple interface types and bridge paths, including conversion, buffering, deinterleaving, and related data movement behaviors.
• Drive verification of advanced interconnect behaviors such as QoS handling, arbitration policy, virtual-network behavior, and transport-level correctness.
• Define high-value directed and constrained-random test scenarios that expose corner cases in coherency, concurrency, ordering, credits, and integration.
• Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve verification methodology, infrastructure, and productivity for the broader interconnect verification effort, not just the block immediately assigned to you.
• Contribute to review quality across specs, verification plans, coverage closure, and debug strategy.

Skills

SystemVerilog

UVM

Debugging

Testbench development

Verification planning

Cross-team collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Python

Job description

SiFive is seeking a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem for high-performance SoCs. You will own complex verification programs spanning data movement, protocol correctness, and subsystem integration across multiple interface types.

This role emphasizes strategy over execution, with collaboration across architecture, design, formal, and software teams to accelerate debug and sign-off.