Staff Design Verification Engineer – Coherent Interconnect

SiFive, Inc.; Massachusetts; On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Comprehensive healthcare

Retirement plans

Paid time off

Job summary

SiFive, Inc. is seeking a Staff Design Verification Engineer to manage verification for a next-generation cache-coherent interconnect subsystem. This role involves planning and executing verification for high-performance SoCs and collaborating with diverse teams to ensure quality.

The ideal candidate will have a strong background in ASIC design verification, with proficiency in SystemVerilog and a deep understanding of cache-coherent systems. SiFive offers a competitive salary and benefits package, fostering innovation and collaboration.

Qualifications

• 7+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience verifying complex protocol behaviors.

Responsibilities

• Own verification planning and execution for a scalable interconnect subsystem.
• Develop and maintain robust verification environments for coherent traffic.
• Collaborate with teams to clarify requirements and accelerate debug.

Skills

SystemVerilog

UVM-based verification

Debugging skills

Protocol adherence

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Python

Job description

SiFive, Inc. is seeking a Staff Design Verification Engineer to manage verification for a next-generation cache-coherent interconnect subsystem. This role involves planning and executing verification for high-performance SoCs and collaborating with diverse teams to ensure quality.

The ideal candidate will have a strong background in ASIC design verification, with proficiency in SystemVerilog and a deep understanding of cache-coherent systems. SiFive offers a competitive salary and benefits package, fostering innovation and collaboration.