Lead Verification Architect, Coherent Interconnect

SiFive, Inc.; Santa Clara (CA); On-site; USD 231,000 - 283,000; Full time

Job summary

SiFive, Inc. is seeking a Principal Design Verification Engineer to lead verification strategy for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

This principal tech-lead role requires defining architecture-aware verification strategies, identifying risk early, solving complex subsystem-level problems, and raising verification quality across the broader interconnect verification effort.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification at principal level.
• Strong hands-on SystemVerilog-based verification and reusable verification infrastructure for complex subsystems.
• Strong understanding of cache-coherent systems, on-chip interconnects, CPU memory-subsystem behavior, and verification of ordering, snooping, and flow-control semantics.
• Deep experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows for complex subsystem-level designs.
• Strong software, scripting, and automation skills in Python or similar languages for scalable DV infrastructure and workflows.

Responsibilities

• Lead verification planning and execution for a cache-coherent interconnect subsystem from block level through subsystem integration and signoff.
• Define verification strategy, test plans, closure criteria, assertions, checkers, scoreboards, stimulus approaches, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, arbitration, QoS, and error handling.
• Drive verification across interface boundaries, bridges, protocol adaptation layers, and related subsystem data-movement paths.
• Develop high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic behavior.
• Partner closely with architecture, RTL, and formal teams to review specifications, close ambiguity early, and improve design debugability and verification completeness before issues harden late in the cycle.
• Drive efficient root-cause analysis across specification, RTL, assertions, test content, and verification infrastructure, and push issues to durable closure.
• Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented verification where appropriate.
• Influence methodology and infrastructure across the broader horizontal interconnect verification effort, not just the block directly assigned to you.
• Mentor engineers and raise the technical bar through reviews, debug leadership, stronger verification practices, and reusable infrastructure.

Skills

SystemVerilog

Verification

Python scripting

Debugging

Technical leadership

Communication

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

UVM

C/C++

Job description

SiFive, Inc. is seeking a Principal Design Verification Engineer to lead verification strategy for a scalable cache-coherent interconnect subsystem used in high-performance CPU and SoC platforms.

This principal tech-lead role requires defining architecture-aware verification strategies, identifying risk early, solving complex subsystem-level problems, and raising verification quality across the broader interconnect verification effort.