Lead Design Verification Architect – Cache-Coherent Interconnect

SiFive; Santa Clara (CA); Hybrid; USD 231,000 - 283,000; Full time

Job summary

SiFive, a leader in RISC-V-based compute, seeks a Principal Design Verification Engineer to steer verification for a cache-coherent interconnect subsystem used in high-performance CPU/SoC platforms.

You will partner with architecture, RTL, formal, and performance teams to ensure protocol correctness, ordering, flow control, and robust integration across interfaces while mentoring engineers and advancing reusable DV infrastructure.

Qualifications

• 12+ years of relevant verification experience for CPU/SoC/ASIC.
• Strong hands-on SystemVerilog-based verification.
• Deep understanding of cache-coherent systems and interconnects.
• Experience crafting verification plans, assertions, checkers, scoreboards, and coverage models.
• Strong debugging and triage skills with efficient issue closure.
• Ability to communicate across architecture, RTL, formal, performance, and verification teams.

Responsibilities

• Lead verification planning and execution for a cache-coherent interconnect subsystem from block level through subsystem integration and signoff.
• Define verification strategy, test plans, closure criteria, assertions, checkers, scoreboards, stimulus approaches, and coverage models for coherent traffic, ordering, backpressure, flow control, buffering behavior, arbitration, QoS, and error handling.
• Drive verification across interface boundaries, bridges, protocol adaptation layers, and related subsystem data-movement paths.
• Develop high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic behavior.
• Partner with architecture, RTL, and formal teams to review specifications, resolve ambiguities, and improve design debugability and verification completeness.
• Drive efficient root-cause analysis across specification, RTL, assertions, test content, and verification infrastructure, and push issues to durable closure.
• Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented verification where appropriate.
• Influence methodology and infrastructure across the broader horizontal interconnect verification effort.
• Mentor engineers and raise the technical bar through reviews, debug leadership, stronger verification practices, and reusable infrastructure.

Skills

SystemVerilog-based verification

Verification strategy

Test planning

Debug and triage

Python scripting

Cross-team collaboration

DV infrastructure

Education

BS/MS/PhD in Electrical Engineering, Computer Engineering, or Computer Science

Tools

SystemVerilog

Python scripting

Verification infrastructure

Job description

SiFive, a leader in RISC-V-based compute, seeks a Principal Design Verification Engineer to steer verification for a cache-coherent interconnect subsystem used in high-performance CPU/SoC platforms.

You will partner with architecture, RTL, formal, and performance teams to ensure protocol correctness, ordering, flow control, and robust integration across interfaces while mentoring engineers and advancing reusable DV infrastructure.