Senior Staff Verification Architect - Interconnect & SoC

SiFive, Inc.; Boston (MA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Comprehensive benefits package

Variable compensation

Equity options

Job summary

SiFive, Inc. is seeking a Senior Staff Design Verification Engineer to lead the verification of advanced cache-coherent interconnect subsystems for high-performance systems on chip (SoCs). This role requires strong expertise in SystemVerilog and significant experience in ASIC/SoC design verification.

The successful candidate will be responsible for defining verification strategies, developing robust environments, and mentoring team members to ensure high-quality verification. Compensation includes base pay, potential incentives, and a competitive benefits package.

Qualifications

• 8+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog.
• Experience creating test plans and debug workflows.

Responsibilities

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem.
• Partner closely with architecture and software teams.
• Mentor engineers and improve verification quality.

Skills

SystemVerilog

Scripting in Python

Debugging complex hardware

Communication skills

Education

BS or MS in Electrical Engineering or related field

Job description

SiFive, Inc. is seeking a Senior Staff Design Verification Engineer to lead the verification of advanced cache-coherent interconnect subsystems for high-performance systems on chip (SoCs). This role requires strong expertise in SystemVerilog and significant experience in ASIC/SoC design verification.

The successful candidate will be responsible for defining verification strategies, developing robust environments, and mentoring team members to ensure high-quality verification. Compensation includes base pay, potential incentives, and a competitive benefits package.