Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive, Inc.; Boston (MA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Comprehensive benefits package

Variable compensation

Equity options

Job summary

SiFive, Inc. is seeking a Senior Staff Design Verification Engineer to lead the verification of advanced cache-coherent interconnect subsystems for high-performance systems on chip (SoCs). This role requires strong expertise in SystemVerilog and significant experience in ASIC/SoC design verification.

The successful candidate will be responsible for defining verification strategies, developing robust environments, and mentoring team members to ensure high-quality verification. Compensation includes base pay, potential incentives, and a competitive benefits package.

Qualifications

• 8+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog.
• Experience creating test plans and debug workflows.

Responsibilities

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem.
• Partner closely with architecture and software teams.
• Mentor engineers and improve verification quality.

Skills

SystemVerilog

Scripting in Python

Debugging complex hardware

Communication skills

Education

BS or MS in Electrical Engineering or related field

Job description

Job Overview

SiFive is looking for a Senior Staff Design Verification Engineer to lead verification of a next‑generation cache‑coherent interconnect subsystem used in high‑performance SoCs. This senior, individual‑contributor role focuses on defining verification strategy, identifying risk early, solving complex subsystem‑level problems, and raising the quality bar across the broader verification effort.

Responsibilities

• Own verification planning and execution for a scalable cache‑coherent interconnect subsystem, from block‑level verification through subsystem integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior.
• Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows.
• Create high‑value directed and constrained‑random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth‑sensitive behavior.
• Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
• Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you.
• Mentor engineers and help raise verification quality across the team.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8+ years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role.
• Strong hands‑on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.
• Strong understanding of cache‑coherent systems, on‑chip interconnects, memory subsystem behavior, and verification of ordering and flow‑control semantics.
• Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high‑performance interconnect standards.
• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
• Strong scripting and automation skills in Python or similar languages.
• Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast‑moving environment.

Preferred Qualifications

• Experience verifying coherent interconnect, cache, or memory‑subsystem IP in high‑performance SoCs.
• Experience with protocol‑conversion or bridge‑heavy subsystems.
• Experience with formal verification, performance‑oriented verification, or emulation / FPGA‑assisted debug.
• Demonstrated technical leadership and the ability to influence verification quality beyond immediate ownership.

Success Criteria

Verification plans are complete, concrete, and aligned to the real architectural risks. Critical bugs are found early, reproduced efficiently, and closed with durable fixes. Coverage and test quality improve meaningfully under your ownership. The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions. Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Additional Information

This position requires a successful background and reference checks, satisfactory proof of the right to work in the United States, and compliance with export‑controlled technology regulations. SiFive is an equal‑opportunity employer and celebrates diversity. As an E‑Verify employer, we use the system to confirm employment eligibility of all new hires per federal law.

Compensation and Benefits

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. It is also eligible for a comprehensive, competitive benefits package that may include healthcare, retirement plans, paid time off, and more.