Senior Staff Verification Architect Interconnect Coherence

SiFive; Boston (MA); On-site; USD 180,000 - 230,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Equity

Job summary

SiFive is seeking a Senior Staff Design Verification Engineer to lead verification of a cache‑coherent interconnect subsystem within high‑performance SoCs. You will shape verification strategy, define test plans, and collaborate across architecture, RTL, formal, and software teams to ensure protocol correctness and QoS.

You will develop scalable verification environments, checkers, scoreboards, and coverage models, while mentoring engineers and improving overall verification quality in a

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8+ years of ASIC/SoC design verification experience at Senior Staff level.
• Hands‑on SystemVerilog experience and reusable verification infrastructure development.
• Understanding of cache‑coherent systems, on‑chip interconnects, memory subsystem behavior, and verification of ordering/flow control semantics.
• Proven test planning, assertions, coverage models, and debug workflows for complex subsystems.
• Strong scripting skills in Python or similar languages.
• Excellent communication and cross‑functional collaboration abilities.

Responsibilities

• Own verification planning and execution for a scalable cache‑coherent interconnect subsystem from block‑level verification through integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, and QoS.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Drive verification across interfaces and bridge paths including CHI, ACE, CXL, and related flows.
• Create directed and constrained‑random scenarios exposing corner cases in coherency and bandwidth‑sensitive behavior.
• Mentor engineers and raise verification quality across the team.
• Collaborate with architecture, RTL, formal, and software teams to resolve ambiguities and improve verification quality.

Skills

SystemVerilog

UVM

Python

Test planning

Debugging

Education

BS/MS in EE/CE/CS

Tools

Verilog

VHDL

Job description

SiFive is seeking a Senior Staff Design Verification Engineer to lead verification of a cache‑coherent interconnect subsystem within high‑performance SoCs. You will shape verification strategy, define test plans, and collaborate across architecture, RTL, formal, and software teams to ensure protocol correctness and QoS.

You will develop scalable verification environments, checkers, scoreboards, and coverage models, while mentoring engineers and improving overall verification quality in a