Senior Staff Design Verification Architect (DDR6)

Renesas

Melbourne (FL)

On-site

USD 130,000 - 190,000

Full time

15 hours ago
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Benefits offered by this job

Medical
Health savings account
Dental
Vision
Life insurance
AD&D
Pet insurance
Paid sick time
Paid holidays
Paid vacation

Job summary

Renesas is seeking a Senior Staff Design Verification Engineer to provide technical leadership for verification of memory interface products for data center, AI, and cloud applications. The role focuses on DDR6 and future generations, leveraging SystemVerilog and UVM to drive verification strategy and test environments.

Candidates should have 10+ years in semiconductor design verification, strong leadership, and proven ability to mentor engineers while coordinating with design and verification

Qualifications

  • 10+ years in semiconductor design verification.
  • Strong SystemVerilog and UVM expertise with testbench development.
  • Proven leadership in verification strategy and mission-critical projects.

Responsibilities

  • Provide technical leadership for verification of complex semiconductor designs at block and system levels.
  • Define and drive verification strategies, test plans, and coverage approaches.
  • Develop and optimize SystemVerilog/UVM verification environments and testbenches.
  • Mentor verification engineers and coordinate with design teams to meet requirements.
  • Communicate risks and status to leadership and stakeholders.

Skills

SystemVerilog
UVM
Verification leadership
Block & system level verification
Debugging

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

UVM testbenches
Verification environments

Job description

Renesas is seeking a Senior Staff Design Verification Engineer to provide technical leadership for verification of memory interface products for data center, AI, and cloud applications. The role focuses on DDR6 and future generations, leveraging SystemVerilog and UVM to drive verification strategy and test environments.

Candidates should have 10+ years in semiconductor design verification, strong leadership, and proven ability to mentor engineers while coordinating with design and verification

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