Senior Memory Verification Lead (DDR6)

Renesas; Tampa (FL); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical and dental benefits

Life insurance and AD&D

Paid time off and holidays

Flexible spending accounts

Job summary

Renesas is seeking a Senior Staff Design Verification Engineer to lead verification for advanced memory interface products for data center, AI, and cloud computing applications. The role focuses on verification strategy, SystemVerilog/UVM environments, and ownership of major verification efforts across blocks and system levels.

The candidate should demonstrate deep semiconductor verification expertise, be comfortable guiding teams, and be open to relocation to support site commitments in

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of related experience in semiconductor design verification.
• Deep experience in semiconductor design verification with leadership of complex verification efforts.
• Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM.
• Experience defining verification strategies and developing verification plans from product and design specifications.
• Strong experience developing and debugging UVM-based verification environments and testbenches.

Responsibilities

• Provide technical leadership for verification of complex semiconductor designs at the block and system level.
• Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
• Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
• Drive verification execution, functional coverage, debugging, and coverage closure.
• Mentor and provide guidance to verification engineers across projects and experience levels.
• Coordinate with technical stakeholders across teams to achieve verification milestones and objectives.
• Communicate verification status, risks, and recommendations to engineering leadership.

Skills

Technical leadership

Mentorship

Communication

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

Tools

SystemVerilog

UVM

Job description

Renesas is seeking a Senior Staff Design Verification Engineer to lead verification for advanced memory interface products for data center, AI, and cloud computing applications. The role focuses on verification strategy, SystemVerilog/UVM environments, and ownership of major verification efforts across blocks and system levels.

The candidate should demonstrate deep semiconductor verification expertise, be comfortable guiding teams, and be open to relocation to support site commitments in