Senior Verification Architect — SystemVerilog/UVM (DDR6)

Renesas Electronics; Orlando (FL); On-site; USD 150,000 - 190,000; Full time

Job summary

Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation memory interface products, including data buffer silicon, in a fast-paced semiconductor environment.

You will drive verification strategy, develop SystemVerilog/UVM testbenches, mentor engineers, and collaborate with RTL and design teams to ensure functionality, performance, and product requirements are met from planning through signoff.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive experience in semiconductor design verification with ownership of complex verification
• Expert-level proficiency with SystemVerilog and UVM
• Experience defining verification strategies and developing verification plans
• Strong experience with functional verification, constrained-random testing, and coverage closure

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Provide technical guidance and mentorship to verification engineers; communicate progress and risks to leadership.

Skills

SystemVerilog

UVM

Semiconductor verification

Technical leadership

Mentoring

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or related field

Job description

Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next-generation memory interface products, including data buffer silicon, in a fast-paced semiconductor environment.

You will drive verification strategy, develop SystemVerilog/UVM testbenches, mentor engineers, and collaborate with RTL and design teams to ensure functionality, performance, and product requirements are met from planning through signoff.